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Testing memory modules in SRAM-based configurable FPGAs

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4 Author(s)
W. K. Huang ; Dept. of Electr. Eng., Fudan Univ., Shanghai, China ; F. J. Meyer ; N. Park ; F. Lombardi

This paper studies the issues involved in testing memory modules (configured as LUTs and RAMs) in FPGAs and proposes new algorithms as this scenario is substantially different from traditional memory testing. Test generation for LUTs and RAMs is analyzed and discussed by reducing the number of configurations as primary objective. It is proved that a memory with n inputs and two programmable modes (given by the LUT-mode and the RAM-mode) can be tested using a total of 4n×2n READs and 2n×2n WRITEs in 2n+1 configurations (in practice n≪5). The conditions by which constant testability of one-dimensional arrays made of memories in a given mode is possible are presented. Hence, to test nr memories with two programmable modes, the number of configurations is given by 3n and the number of tests is 8n×2n. The application to Xilinx and Altera FPGAs is presented

Published in:

Memory Technology, Design and Testing, 1997. Proceedings., International Workshop on

Date of Conference:

11-12 Aug 1997