Scheduled System Maintenance on May 29th, 2015:
IEEE Xplore will be upgraded between 11:00 AM and 10:00 PM EDT. During this time there may be intermittent impact on performance. For technical support, please contact us at onlinesupport@ieee.org. We apologize for any inconvenience.
By Topic

A low-power high storage capacity structure for GaAs MESFET ROM

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Kanan, R. ; Electron. Lab., Swiss Federal Inst. of Technol., Lausanne, Switzerland ; Declercq, M. ; Guyot, A. ; Hochet, B.

Gallium Arsenide (GaAs) is used in the design of high speed systems; however, it is difficult or impossible to realize high-capacity ROMs, because of subthreshold currents and an unacceptable power dissipation. This paper describes a new approach which overcomes the above problems and allows the realization of both low-power and high storage capacity ROMs in GaAs. In this technique, called DDM (Divided Decoder Matrix), low-power operation is obtained by powering down the parts which are not situated in the addressing path, while high-storage capability is obtained by limiting the leakage currents in the ROM matrix. In addition, this approach improves the noise margin of the DCFL gate with the increase of the fan-in. As an application of the DDM technique, an 8 Kbit MESFET ROM has been designed with a standard 0.6 μm-gate MESFET process. The ROM has a typical access time of 1.2 ns and a power dissipation of 60 mW

Published in:

Memory Technology, Design and Testing, 1997. Proceedings., International Workshop on

Date of Conference:

11-12 Aug 1997