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Formal verification of memory arrays using symbolic trajectory evaluation

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2 Author(s)
M. Pandey ; Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA ; R. E. Bryant

Verification of memory arrays is an important part of processor verification. Memory arrays include circuits such as on-chip caches, cache tags, register files, and branch prediction buffers having memory cores embedded within complex logic. These circuits are typically custom designed at the transistor-level to optimize area and performance. This makes it necessary to verify them at the transistor-level. Conventional array verification approaches are based on switch-level simulation. Such approaches do not work for arrays as it is infeasible to simulate the astronomical number of simulation patterns that are required to verify these designs. Therefore, formal methods are required to ensure the correctness of memory arrays. This paper describes the formal verification technique of Symbolic Trajectory Evaluation (STE), and its application to verify memory arrays. The paper describes techniques to overcome the limitations of STE in verifying large complex memory arrays. It shows how exploiting symmetry allows one to verify systems several orders of magnitude larger than otherwise possible. The results of verifying SRAM arrays, including a 256 Kbit circuit having over 1.5 million transistors, are presented. The paper also shows how judicious Boolean encodings can be used with STE to efficiently verify CAMs

Published in:

Memory Technology, Design and Testing, 1997. Proceedings., International Workshop on

Date of Conference:

11-12 Aug 1997