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High speed circuit techniques in a 150 MHz 64 M SDRAM

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7 Author(s)
Lines, V. ; MOSAID Technol. Inc., Canada ; Abou-Seido, M. ; Mar, C. ; Achyuthan, A.
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This paper outlines three methods used to decrease the access time in a 64 M SDRAM. The access time from the read command, Taa, is reduced by the use of a novel column redundancy scheme with easy programming and by the use of current sensing in the data output path. The access time from the clock, Tac, is reduced by the use of a digital DLL whose functionality can be tested with on chip test functions

Published in:

Memory Technology, Design and Testing, 1997. Proceedings., International Workshop on

Date of Conference:

11-12 Aug 1997