Skip to Main Content
Memory, the unit responsible for data and information storage, is the most populated module in present electronic devices. High-speed devices use Static Random Access Memory (SRAM) for data storage. The requirement in present scenario is low power devices. Keeping this point in view, this paper proposes Charge Recycling (CR) on 9T CMOS SRAM. The Proposed and conventional 64-bit SRAM has been designed and simulated for 250nm, 180nm and 130nm CMOS technologies. The 64-bit memory is organized in 8 × 8 form (i.e. 8 rows and 8 columns). Simulation results show the reduction in average write power is 78.22%, 77.15% and 66.66% at 250nm, 180nm and 130nm CMOS technologies respectively when compared with simulation results of conventional 6T SRAM for the same technologies. Simulation has been done at 100MHz and at 1.8 volts rail-to-rail voltage.