By Topic

Design of low power and high performance router using dynamic power reduction technique

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)

This paper describes about the design methodology for reducing router power consumption with the aid of RTL clock gating technique. It causes inactive clocked elements to have clock gating logic (automatically by using cadence tool) which reduces power consumption on those elements to zero when the values stored by those elements are not changing. This technique allows a variety of features such as easily configurable, automatically implemented clock gating which allows maximal reduction in power requirements with minimal designer involvement and software involvement. In this paper, source code was written in Verilog (Hardware Descriptive language) and it was synthesized in Xilinx 9.1i version, simulated in Modelsim 6.6 version and clock gating was applied by using Cadence.

Published in:

Devices, Circuits and Systems (ICDCS), 2012 International Conference on

Date of Conference:

15-16 March 2012