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A 1.2V 80MS/S sample and hold for ADC applications

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2 Author(s)
Reddy, Y.S.G. ; Dept. of Electron. & Commun. Eng., Anurag Eng. Coll., Kodad, India ; Liter, S.

This Paper presents the design of low voltage sample and hold amplifier for analog to digital converter applications. The proposed design uses double sampling technique to increase the sampling rate, reliable bootstrap switch to reduce switch on resistance and to extend linear range of switch. A rail-to-rail ICMR op-amp, is used to extend the input operating range. The designed sample and hold operates at 80MS/s from 1.2V supply. The circuits are designed using CSM 0.18um technology in cadence environment and power consumption estimated was 4.15mW.

Published in:

Devices, Circuits and Systems (ICDCS), 2012 International Conference on

Date of Conference:

15-16 March 2012