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The developed associative-memory architecture utilizes a mapping operation of the Hamming distances into frequency space with ring oscillators programmable in discrete frequency steps. As a result fast word-parallel search of the nearest Hamming distance with low power consumption is obtained. Additionally, high robustness against fabrication-related variations of the MOSFET characteristics is achievable by design because the size of the frequency steps is a freely selectable design parameter which can be adjusted to compensate the variation magnitude. A quantitative analysis of within-die variation effects on the reliability of the associative-memory architecture is presented and guidelines for the choice of the design parameters at a given magnitude of the variation effects are derived. Feasibility and performance of this associative-memory architecture are experimentally evaluated with a VLSI design in 180 nm CMOS technology containing 64 reference patterns each consisting of 256 bits. The fabricated chip is correctly operating down to low supply voltages (Vdd) of 0.7 V. The power dissipation is less than 36.5 mW and 307 μW at supply voltages of 1.8 V (nominal supply) and 0.7 V, respectively. Measured search reliability is found to be in agreement with measured variations of the important design parameters and expectations from the variation analysis. In comparison to previously reported digital associative-memory designs, the achieved power dissipation is more than 5 times smaller, while the average search speed is only slightly improved. For Vdd = 1.8 V the search time ranges from a minimum of 50 ns at Hamming distance 0 to a maximum of 245 ns for the largest Hamming distance 255.
Date of Publication: June 2012