By Topic

Measurement, modeling, and simulation of flip-chip CMOS ASIC simultaneous switching noise on a multilayer ceramic BGA

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
J. P. Libous ; CMOS ASIC Technol. Dev., IBM Microelectron., Endicott, NY, USA ; D. P. O'Connor

This paper presents the simultaneous switching noise (SSN) measurements, modeling, and simulation of a flip-chip complementary metal-oxide-semiconductor (CMOS) application-specific integrated circuit (ASIC) test chip on a multilayer ceramic ball grid array (CBGA) package. Technology and design features of the chip and package test vehicles are described. Time-domain noise measurement techniques and results are presented in detail. Circuit modeling and simulation methodologies are developed and validated by strong correlation between measurement and simulation results

Published in:

IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B  (Volume:20 ,  Issue: 3 )