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Process Variation Tolerant All-Digital 90 ^{\circ} Phase Shift DLL for DDR3 Interface

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8 Author(s)
Heechai Kang ; Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea ; Kyungho Ryu ; Dong Hoon Jung ; Donghwan Lee
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An all-digital 90° phase shift delay lock loop (DLL) is presented, which is robust against the delay mismatch caused by process variation. Each of the four 90° phase shift blocks accurately aligns its output to a 90° shifted phase using its own ring oscillator and locking delay code. It is analytically proved that the phase shift accuracy of the proposed 90° phase shift block is always higher than that of the conventional all-digital 90° phase shift DLL. The harmonic locking problem is prevented by a ring oscillator and a counter. An area-efficient binary-to-thermometer converter is proposed to reduce the area overhead caused by the delay-line control logic. A fast operating frequency with a finer resolution is achieved through the fine delay range selector and the resistance controlled fine delay unit. The proposed 90° phase shift DLL is implemented using a 45-nm CMOS process. The phase shift accuracy errors at the 90° and 270° phases are 0.43° and 1.01°, respectively, when the maximum locking delay code difference between the four 90° phase shift delay lines corresponds to ±9.97° at 800 MHz. It proves that the DLL corrects the significant phase error caused by process variation. The power consumption is 3.3 mW at 800 MHz.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:59 ,  Issue: 10 )

Date of Publication:

Oct. 2012

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