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A stoppable four-phase clock generator for low-power and low-noise applications

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4 Author(s)
Mounir Zid ; Electronics and Micro-Electronics Laboratory, Faculty of Sciences of Monastir (FSM), Monastir, Tunisia ; Rached Tourki ; Alberto Scandurra ; Carlo Pistritto

In this work we present a low-power, low-area and high-speed fully CMOS quadrature clock generator for low-power and low-noise on-chip devices. The device is constructed around a couple of differential prescalers for high speed frequency division and four duty cycle adjusters to set the duty cycle of the produced clock signals at 50% of the clock period. The circuit was implemented with the STMicroelectronics 65 nm process technology using only 125 transistors and it occupies an active area of under 2.34 μm2. With a power supply of 1.1 V the complete circuit consumes 89.56 μW at room temperature.

Published in:

ICM 2011 Proceeding

Date of Conference:

19-22 Dec. 2011