By Topic

A new efficient self-checking Hsiao SEC-DED memory error correcting code

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Aymen, F. ; Electron. & Microelectron. Lab., Monastir, Tunisia ; Belgacem, H. ; Chiraz, K.

Interest in on-line error detection continues to grow as VLSI circuits increase in complexity. Concurrent checking is increasingly becoming a desirable characteristic thanks to its ability to detect transient faults that may occur in a circuit during normal operation. Accordingly, Concurrent Error Detection (CED) techniques allow the detection of transient faults, which probably not be detected in off-line testing, since they may not occur in test mode. Actually, memories occupy 90% of the SOC area. As they are a fault sensitive, adding error correcting codes (ECC) structures is becoming conventional to enhance the reliability. Hence, designing the ECC logic must ensure not only responding to nanotechnology requirements as high density, reduced power consumption and faster calculation delays but also to be a fail-safe. In this paper, a new self-checking error correcting SEC-DED code architecture is presented. We added the self-checking capability to the SEC-DED circuit using a self-checking differential XOR implemented in Complementary Pass Transistor Logic (CPL). We have selected the Hsiao code to design an efficient SEC-DED.

Published in:

Microelectronics (ICM), 2011 International Conference on

Date of Conference:

19-22 Dec. 2011