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Interest in on-line error detection continues to grow as VLSI circuits increase in complexity. Concurrent checking is increasingly becoming a desirable characteristic thanks to its ability to detect transient faults that may occur in a circuit during normal operation. Accordingly, Concurrent Error Detection (CED) techniques allow the detection of transient faults, which probably not be detected in off-line testing, since they may not occur in test mode. Actually, memories occupy 90% of the SOC area. As they are a fault sensitive, adding error correcting codes (ECC) structures is becoming conventional to enhance the reliability. Hence, designing the ECC logic must ensure not only responding to nanotechnology requirements as high density, reduced power consumption and faster calculation delays but also to be a fail-safe. In this paper, a new self-checking error correcting SEC-DED code architecture is presented. We added the self-checking capability to the SEC-DED circuit using a self-checking differential XOR implemented in Complementary Pass Transistor Logic (CPL). We have selected the Hsiao code to design an efficient SEC-DED.