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In this paper, authors propose a new Second Order Differential Power Analysis (SO-DPA) countermeasure for AES cipher. While published results for SO-DPA are proposing multiple masking solutions and the design of two independent True Random Number Generator (TRNG), the proposed design in this paper uses only one TRNG and combines a simple masking solution with the Correlated Power Noise generator (CPNG) countermeasure. This design optimization led to silicon area overhead reduction by 4% without including the area of the TRNG. Experimental results of FPGA-based hardware implementation are presented to highlight the robustness of the proposed design and its reduced complexity implementation.