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A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme

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28 Author(s)
Kyomin Sohn ; Samsung Electron., Hwasung, South Korea ; Taesik Na ; Indal Song ; Yong Shim
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A higher performance DRAM is required by the market due to the increasing of bandwidth of networks and the rise of high-capacity multimedia content. DDR4 SDRAM is the next-generation memory that meets these demands in computing and server systems. In comparison with current DDR3 memory, the major changes are supply voltage reduction to 1.2V, pseudo open drain I/O interface, and data rate increase from 1.6 to 3.2Gb/s. To achieve high performance at low supply voltage and reduce power consumption, this work introduces new functions and describes their implementation. Data bus inversion (DBI) is employed for high-speed transactions to reduce power consumption of I/O and SSN noise. Dual-error detection, which adopts cyclic redundancy check (CRC) for DQ, and command address (CA) parity is designed to guarantee reliable transmission. GDDR5 memory also has DBI and CRC functions [1], but in this work, these schemes are implemented in a way that reduces area overhead and timing penalty. Besides these error-check functions, an enhanced gain buffer and a PVT-tolerant fetch scheme improve basic receiving ability. To meet the output jitter requirements of DDR4 SDRAM, the type of delay line for DLL is selected at initial stage according to data rate.

Published in:

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International

Date of Conference:

19-23 Feb. 2012