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Optimization of fT, BVCEO and β with selectively implanted collectors in BiCMOS technology

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1 Author(s)
M. G. Guvench ; Univ. of Southern Maine, Gorham, ME, USA

This paper shows that by implanting the collector of its NPN transistors with N-type impurities and by choosing the right combination of the dopants, dose and energy, fT can be improved significantly in a BiCMOS process. The improvement is mask selectable, i.e., it allows two sets of transistors: (1) SIC, “Selectively Implanted Collector” transistors and (2) the original process NPNs which are unchanged, to be created side by side. Simulations done by incorporating the SIC implant on the experimentally verified numerical model simulations of the original process showed that fTmax can be improved from 13.5 GHz to 21 GHz in a 0.6-0.8 μm BiCMOS process. It is also shown that the SIC implanted transistors, when optimum dose and energy values are used, will yield transistors whose β will not differ more than 30% from the β the mainstream BiCMOS process yields

Published in:

University/Government/Industry Microelectronics Symposium, 1997., Proceedings of the Twelfth Biennial

Date of Conference:

20-23 Jul 1997