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A 622 Mbps ATM physical layer ASIC and its “design for test” methods

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4 Author(s)

A 622 Mbps ATM physical layer ASIC design is described. This ASIC performs the full 622 Mbps ATM physical layer functions according to the ITU-T I.432 and ATM Forum UNI standards. The cells are processed at 77.76 MHz speed but most of the other STM related circuits run at te 19.44 MHz clock rate. Each functional block is explained with its robust synchronization mechanism among other processing blocks. The design aspects and techniques for the ASIC test are explained for scan test and additional functional test in a reduced frame mode which was specially designed for this ASIC. Most of the basic functions were verified through loop-back test including fiber loops

Published in:

Computers and Communications, 1997. Proceedings., Second IEEE Symposium on

Date of Conference:

1-3 Jul 1997

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