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A dual-loop architecture employs eight distributed microregulators (UREGs) to achieve load response times below 500 ps in 45-nm SOI CMOS. The trip point of an asynchronous comparator inside each UREG is tuned for high DC accuracy with a local charge pump, which receives UP/DOWN currents from a slow outer feedback loop. The feedback through the charge pumps also ensures balanced load sharing among the UREGs. Two techniques are introduced to reduce the output ripple generated by switching the pMOS passgate on and off: hybrid fast/slow passgate control (in which the DC portion of the load current is supplied by a parallel output device with slew-rate-limited gate drive) and pMOS strength calibration (which adjusts the active width of the passgate to compensate for PVT variations). The distributed regulator system is integrated into a DDR3 I/O core and supplies power to CMOS delay lines used for clock-to-data deskewing. Each of the eight UREGs is sized to provide up to 5.3 mA of load current and occupies an area of 55 × 60 μm2. The measured DC load regulation is better than 10 mV down to an 85-mV dropout voltage. Jitter readings of the CMOS delay lines indicate output noise close to 28 mVpp.