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The paper proposed a reconfigurable parallel hardware structure targeted at linear feedback shift register. As to the reconfigurable performance, the structure could reconfigure different LFSR in various stream ciphers. As to the parallel performance, the proposed hardware structure could support parallel update of LFSR sequences in one clock cycle. Besides, with the tradeoff between the flexibility and high performance, the paper adopted reconfigurable and parallel technology to design a feedback shift register hardware structure, the thesis synthesized the design in 0.18μm CMOS process. The result proves that the critical path of reconfigurable feedback shift register with 256 lengths, random feedback taps, 32 parallelizability is 7.63ns, the throughput rate can achieve 4.09Gbps for LFSR(256 lengths).