By Topic

ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Jinn-Shyan Wang ; Department of Electrical Engineering, Chung-Cheng University, Chia-Yi 620, Taiwan ; Yung-Chen Chien ; Jia-Hong Lin ; Chun-Yuan Cheng
more authors

This work proposes an ADDLL/VDD-biasing co-design methodology for variation-tolerant designs. A modified ADDLL behaves as a variability sensor in the beginning of operation, and the sensing result is used by a VDD-biasing circuit to adjust the VDD of a loaded design for performance calibration. During normal operation, the ADDLL is reused as a de-skewing element for the calibrated design. With this methodology, not only the performance of the loaded design but also that of the ADDLL can be effectively adjusted toward their design specifications even under serious process variations.

Published in:

ASIC (ASICON), 2011 IEEE 9th International Conference on

Date of Conference:

25-28 Oct. 2011