Referenced Items are not available for this document.
We have applied thoroughly clock gating technique to the SH-4A FPU (Floating Point Unit) core [1] while still keeping it co-operates with CPU core. As a result, 97% flip-flops in FPU is gated. And the power consumption is saved up to 78.11% in FPU, corresponding to 17.02% power consumption reducing of total CPU and FPU core in Dhrystone benchmark. This paper introduces such approach in which the clock is controlled thoroughly and provided to FPU only when the FPU instruction is under-processing.
Published in:
ASIC (ASICON), 2011 IEEE 9th International Conference on
Date of Conference: 25-28 Oct. 2011
- Page(s):
- 39 - 42
- ISSN :
- 2162-7541
- E-ISBN :
- 978-1-61284-191-5
- Print ISBN:
- 978-1-61284-192-2
- INSPEC Accession Number:
- 12575823
- Conference Location :
- Xiamen
- Digital Object Identifier :
- 10.1109/ASICON.2011.6157117
- Product Type:
- Conference Publications
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