Low power shift registers for megabits CMOS image sensors

This study investigated the design of low-power shift registers (SR) for CMOS image sensors. First we analyzed a classic clock-gating-control-unit (CGCU) based SR, and showed that besides inefficient area utilization, the CGCU SR is subject to high power consumption due to coupling noise and leakage current. In this work, we developed new design techniques called LGCS (locally gated clock signals) and EDCD (equally divided clock domains) to construct a low-power SR. Experimental results show that the new SR achieves a 14X power reduction and a 39% area reduction compared to the CGCU SR.