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The isolation techniques against substrate noise coupling utilizing through silicon via (TSV) process are described. The trench shape TSV encloses the RF circuit on a SoC chip to improve the isolation between digital circuits and the RF circuits without constraints of on-chip interconnect above first metal as the TSV is connected to the grounded 1st metal from the back side of the substrate. The analysis with simplified model is proposed to show the effect of the proposed isolation techniques. Mesh circuit model is applied to simulate the noise distribution in detail. Various test patterns are fabricated on a CMOS silicon substrate with resistivity of 10 Ωcm. The measurement pattern of H-shaped TSV confirms about 30 dB and 40 dB improvement at 100 MHz and 1 GHz respectively, which is much better than conventional isolation techniques such as guard ring, Deep N-well and DTI. The combinational pattern with TSV, DTI and high resistive layer shows 60 dB improvement of the isolation. Proposed isolation techniques are useful for substrate noise coupling of future RF/mixed-signal SoCs.