By Topic

Two-Step Write Scheme for Reducing Sneak-Path Leakage in Complementary Memristor Array

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Chul-Moon Jung ; School of Electrical Engineering , Kookmin University, Seoul, Korea ; Jun-Myung Choi ; Kyeong-Sik Min

In this paper, a new two-step write scheme is proposed to minimize sneak-path leakage in complementary memristor (CM) array, where no selection device is needed. When R RESET/R SET = 100, the new two-step write scheme can increase the array size of CMs 10 times larger than the conventional write. If R RESET/R SET is increased to 500, we can increase the passive array size up to 1000 × 1000 with maintaining the read sensing margin lager than 10% of VDD. The two-step write scheme will be very essential in realizing passive cross-point array without any selection device that is known to be the ideal architecture for future 3-D memories.

Published in:

IEEE Transactions on Nanotechnology  (Volume:11 ,  Issue: 3 )