By Topic

VLSI Architecture for a Reconfigurable Spectrally Efficient FDM Baseband Transmitter

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Whatmough, P.N. ; Electr. & Electron. Eng. Dept., Univ. Coll. London, London, UK ; Perrett, M.R. ; Isam, S. ; Darwazeh, I.

Spectrally efficient FDM (SEFDM) systems employ non-orthogonal overlapped carriers to improve spectral efficiency for future communication systems. One of the key research challenges for SEFDM systems is to demonstrate efficient hardware implementations for transmitters and receivers. Focusing on transmitters, this paper explains the SEFDM concept and examines the complexity of published modulation algorithms, with particular consideration to implementation issues. We then present two new variants of a digital baseband transmitter architecture for SEFDM, based on a modulation algorithm which employs the discrete Fourier transform (DFT) implemented efficiently using the fast Fourier transform (FFT). The algorithm requires multiple FFTs, which can be configured either as parallel transforms, which is optimal for throughput or using a multi-stream FFT architecture, for reduced circuit area. We propose a simplified approach to IFFT pruning for pipeline architectures, based on a token-flow control style, specifically optimized for the SEFDM application. Reconfigurable implementations for different bandwidth compression ratios, including conventional OFDM, are easily derived from the proposed implementations. The SEFDM transmitters have been synthesized, placed and routed in a commercial 32 nm CMOS process technology and also verified in FPGA. We report circuit area and simulated power dissipation figures, which confirm the feasibility of SEFDM transmitters.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:59 ,  Issue: 5 )