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This paper presents a study of hardware implementations of Elliptic Curve Cryptography (ECC) in Wireless Sensor Networks (WSN). A critical study of the underlying finite field, representation basis, occupied chip area, consumed power, and time performances of these implementations is conducted. The study shows that most of the reviewed implementations were implemented on Application Specific Integrated Circuits (ASIC) and only one was implemented on Field Programmable Gate Array (FPGA). Most of these implementations were implemented over the binary fields GF(2m) and using polynomial basis representation.