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This paper discusses the problems which are the power consumption of gate drive circuit and voltage oscillation of source-to-gate voltage in the power converters using high-frequency power devices. The circuit parameters design were executed in terms of (i) power consumption of the gate drive circuit at FET and (ii) voltage oscillation of source-to-gate voltage at FET. As for (i), it is confirmed that the gate drive circuit can reduce the power consumption of it from 250 mW to 10 mW. As for (ii), it formulated the relationship between the circuit parameters and the voltage oscillation by circuit analysis. However, a gap of voltage oscillation occurs for the calculation results. The simulation was performed in order to presume this gap of voltage oscillation factor. Then, it confirmed that gap of the experimental results and the calculation results could be reduced to about 2V.