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3D through silicon via (TSV) and vertical stacking technologies have become key enablers in the move towards high density, high functionality 3D integrated circuits. The need to address strain, warpage, delamination, etc. in Systems on Chip or Systems in Package (SoC/SiP) is recognised in the International Technology Roadmap for Semiconductors (IRTS 2009). This paper describes the implementation of a novel technique called 3-dimensional surface mapping (3DSM) for the non-destructive measurement of in situ strain and wafer die warpage in thin, chip embedded Quad Flat Nonlead (QFN) packages. X-Ray Diffraction Imaging (XRDI) is used, in conjunction with 3DSM, to obtain high resolution (~3 μm) strain/warpage maps and qualitative information on the nature and extent of the strain fields in completely packaged chips. QFN packages were examined after 3 different stages of the manufacturing process: chip attach, via electroplating, and post-production as a means of demonstrating the potential for this technique to provide quick feedback towards process improvement and thus reduce major sources of die warpage.