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Ultra-low power and low voltage circuit design for next-generation power-aware LSI applications

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1 Author(s)
Tetsuya Hirose ; Department of Electrical and Electronic Engineering, Kobe University, 1-1 Rokkodai, Nada, Kobe 657-8501, Japan

In this paper, we propose delay-compensation techniques for ultra-low power subthreshold digital circuits and a nano-ampere CMOS current reference circuit that is tolerant to threshold voltage variations. Delay in digital circuits that are operated in the subthreshold region of a MOSFET changes exponentially with variations in threshold voltage. Therefore, compensation techniques are required to mitigate the variation. To achieve robust operation for extremely low voltage digital circuits, threshold-voltage monitoring and supply-voltage scaling techniques are developed. By monitoring the threshold voltage of each LSI chip and exploiting the voltage to supply voltage to subthreshold digital circuits, variations in delay time can be suppressed significantly. Monte Carlo SPICE simulation demonstrates that delay-time distribution can be improved from log-normal to normal. The coefficient of variation for the proposed technique is 31%.

Published in:

SoC Design Conference (ISOCC), 2011 International

Date of Conference:

17-18 Nov. 2011