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Design consideration for 60 GHz SiGe power amplifier with ESD protection

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3 Author(s)
Keping Wang ; Div. of Circuit & Syst., Nanyang Technol. Univ., Singapore, Singapore ; Kaixue Ma ; Kiat Seng Yeo

This paper describes a 60 GHz high gain power amplifiers (PA) designed in a 0.18-μm SiGe BiCMOS technology. It consists of four cascode stages with inter-stage matching implemented by the conductor-backed coplanar waveguide (CBCPW) structures and metal-insulator-metal (MIM) capacitors. A double-stub low Q input matching network is design to achieve wideband input matching. Since one of double-stub is open stub, the S11 can easily be tuned by trimming after fabrication. Load-pull simulation generates the optimal load impedance. A wideband harmonic rejection ESD is introduced to simultaneously reject the harmonics and achieve ESD protection. Simulation result shows that the maximum gain is 35.4 dB with 3 dB bandwidth 55-69 GHz. The S11 is 1-10 dB in the 50-80 GHz. The output P1dB is 6.7 dBm and the saturated output power Psat is 8.9 dBm. The peak PAE is 12.8%. The chip size is 1050×280 μm2. It consumes 60mW from a 1.8V supply.

Published in:

SoC Design Conference (ISOCC), 2011 International

Date of Conference:

17-18 Nov. 2011