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In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. The tradeoff between power consumption and speed performance has become a very important concern in circuit design process. It is especially critical when dealing with large data set, whereby the system is degraded in terms of power and speed. By adopting an emerging concept in VLSI design and test, i.e. Error-Tolerance (ET) whereby the correctness is compromised, a large reduction in in power consumption and improvement in speed can be achieved. In this paper, we present a novel low-power and highspeed Probabilistic Adder for Error-Tolerant Applications (ETA) Type III design called ETAIII. The proposed ETAIII is an enhancement of our earlier design, ETAI .