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Compaction with general synchronous timing

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2 Author(s)
V. H. Allan ; Dept. of Comput. Sci., Utah State Univ., Logan, UT, USA ; R. A. Mueller

In current microcode generation systems, one simplification that is frequently made is to assume an absence of timing restrictions. It is critical that timing is considered when the target architecture involves branch delays, volatile registers, or microoperations requiring multiple microinstructions to complete. A general form for representing synchronous timing in clocked microarchitectures and methods of compacting data-dependency graphs with general timing are described

Published in:

IEEE Transactions on Software Engineering  (Volume:14 ,  Issue: 5 )