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Performance innovation in the IBM zEnterprise 196 processor

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5 Author(s)
D. F. Greiner ; IBM Silicon Valley Laboratory, IBM Systems and Technology Group, San Jose, CA, USA ; M. M. Mitran ; T. J. Slegel ; C. R. Walters
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The IBM zEnterprise® 196 achieves substantial performance gains over prior designs across the full spectrum of workloads being run on today's enterprise information technology systems, ranging from large data-intensive transaction processing workloads to central processing unit-intensive business applications. Each of these required innovations in the design of the hardware, software, and instruction-set architecture (ISA) with performance gains coming from several sources: the out-of-order microprocessor core design, the multilevel cache structure, new ISA facilities, and additional ISA extensions to enable efficient scaling of large multiprocessor operating system images. These enhancements were achieved through collaborative development among hardware, software, compiler, architecture, and performance analysis teams. This paper describes the performance contributions from these sources, with particular focus on the new architectural facilities.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:56 ,  Issue: 1.2 )