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High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology

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2 Author(s)
Nan, Haiqing ; Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA ; Ken Choi

In this paper, three high performance, low cost and robust latches (referred to as HLR, HLR-CG1, and HLR-CG2) are proposed in 45 nm CMOS technology. The proposed latches are completely insensitive to transient faults at their internal nodes and output node independent of the size and technology of the CMOS transistor. The proposed latches tolerate transient faults regardless of the energy of the striking particle. The proposed latches offer faster speed, higher reliability to transient faults with lower costs regarding power and area than most of the latches recently proposed in the literature. The proposed designs demonstrate that the power-delay-product benefit is 13 times on average compared to previous robust latches including standard latch.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:59 ,  Issue: 7 )

Date of Publication:

July 2012

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