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Since the topology of neural networks is very crucial to the performance, the reconfigurable ability of the neural network hardware is very important. Therefore, this paper proposes an efficient architecture to implement the reconfigurable back propagation based neural network (BPNN). To further reduce the hardware, this paper adopts the resource sharing method. Finally, Xilinx - ISE is used to synthesize BPNN into the field-programmable gate arrays (FPGA) in experiments.