By Topic

PRAM cell technology and characterization in 20nm node size

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

13 Author(s)
M. J. Kang ; New Memory Lab., Semiconductor Research Center, Samsung Electronics Co. Ltd., San #16, Banwol-Dong, Hwasung-City, Gyunggi-Do 445-701, Korea ; T. J. Park ; Y. W. Kwon ; D. H. Ahn
more authors

We reported characteristics of 20nm PRAM cell. Optimization of diode integration process and improved implantation technology were used to satisfy the required diode on-current (Ion) with low off-current (Ioff). Confined cell structure and novel bottom electrode (BE) materials were developed to reduce a reset current (Ireset) below 100uA. Using the advanced technologies, we successfully produced fully integrated 20nm node size PRAM device for the first time.

Published in:

Electron Devices Meeting (IEDM), 2011 IEEE International

Date of Conference:

5-7 Dec. 2011