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To prevent soft errors from causing data corruption, memories are typically protected with error correction codes (ECCs). For example, single-error correction (SEC) codes that can correct one error in a memory word are commonly used. More advanced ECCs are also used when additional protection is needed. While the error correction capability of a code is important, it is also important to detect errors that cannot be corrected to avoid silent data corruption. For example, in a SEC code, a double error may be misinterpreted as a single error and corrected, ending with an incorrect word. For that reason, codes that can also detect double errors are preferred. Those are known as SEC double-error-detection codes. The same reasoning applies to more advanced ECCs. Among those, difference set (DS) codes have shown interesting properties that enable an efficient implementation in terms of decoding latency and complexity. However, existing decoders for DS codes focus on error correction only, making them less attractive for memory protection. In this paper, modified decoding algorithms for DS codes are proposed that, in addition to error correction, provide error detection when the number of correctable bit errors is exceeded by one. This combined error detection and correction capability of the modified decoder makes the proposed scheme a promising option for memory applications. HDL implementation and synthesis results are included, showing that the proposed techniques can be efficiently implemented.