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Adaptation of Standard RT Level BIST Architectures for System Level Communication Testing

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2 Author(s)
Nemati, N. ; Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran ; Navabi, Z.

Test and testability are essential concerns for design in any abstraction level, and are even more challenging for high level designs. Because of complexity of today's designs, design at ESL (electronic system level) using transaction level modeling (TLM) has become a focal point of today's system level designers. However, there are no standard test methods or conventions proposed for this level of abstraction. Built-In Self-Test is a conventional DFT method, well defined in gate level and RT level. In this work by inspiration from the standard RTL BIST architectures, and finding similarities in TLM-2 designs and the RTL designs being tested by standard RTL BISTs, a number of TLM-2 BIST architectures are proposed. The overhead of inserting these BISTs in the original design is calculated.

Published in:

Test Symposium (ATS), 2011 20th Asian

Date of Conference:

20-23 Nov. 2011