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While raising the level of abstraction in design methodologies is uniformly accepted as desirable, raising Design For Test of complex VLSI chips is still challenging for both analysis and implementation. Still, testing logic can be described at the RT-level, and inserting it before synthesis has many advantages, among which the ability to debug testability issues early in the design flow, and leveraging the optimization done by the synthesis tool. But inserting DFT logic such as a full-scantest logic before synthesis brings its own challenges: the earlier it is inserted in the flow, the harder it is to provide low-overhead insertion. In this work, we combine the use of a lightweight synthesis with graph models for inferring logical proximity information from the design, and then use classic approximation algorithms for the traveling salesman problem to determine the scan-stitching ordering. We show how this procedure allows the decrease of the cost of both scan analysis and implementation, by measuring total wire length on placed and routed benchmark designs, both academic and industrial.