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Atomistic nanoelectronic device engineering with sustained performances up to 1.44 PFlop/s

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4 Author(s)
Mathieu Luisier ; Network for Computational Nanotechnology, Purdue University, West Lafayette, IN 47907, USA ; Timothy B. Boykin ; Gerhard Klimeck ; Wolfgang Fichtner

We present a multi-dimensional, atomistic, quantum transport simulation approach to investigate the performances of realistic nanoscale transistors for various geometries and material systems. The central computation consists in solving the Schrodinger equation with open boundary conditions several thousand times. To do that, a Wave Function approach is used since it can be relatively easily parallelized. To further improve the computational efficiency, three additional levels of parallelization are identified, the work load is optimally balanced between the CPUs, computational interleaving is applied where possible, and a mixed precision scheme is introduced. Using two different device types, a high electron mobility and a band-to-band tunneling transistor, sustained performances up to 1.28 PFlop/s in double precision (55% of the peak performance) and 1.44 PFlop/s in mixed precision are reached on 221,400 cores on the CRAY-XT5 Jaguar at Oak Ridge National Lab.

Published in:

2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC)

Date of Conference:

12-18 Nov. 2011