A scalable hybrid verification system based on HDL slicing

For functional verification, logic emulators offer speed of execution while software simulators provide full observability and advanced debugging techniques. Hybrid functional verification systems, which run long test sequences in an emulator and upon error detection, transparently switch-over to simulation based debugging are extensively used. These systems suffer from scalability problem since simulators cannot handle large designs efficiently, restricting their application to only relatively small designs. This paper presents a novel methodology to achieve scalability in such systems. The full design is run on emulator, but on error detection only a smaller and pre-computed HDL slice corresponding to the property under verification is loaded on simulator for debugging, instead of the full unsliced design. Application of the system to verification of real complex System-on-Chips (SoC) show the effectiveness of our approach.