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Modular equivalence verification of polynomial datapaths with multiple word-length operands

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2 Author(s)
Bijan Alizadeh ; Electrical and Computer Engineering Department, University of Tehran, Iran ; Masahiro Fujita

In this paper, we extend Modular Horner Expansion Diagram (Modular-HED) as a canonical polynomial representation to verify polynomial functions with multiple bit-width operands from Z2n1×Z2n2...×Z2nd to Z2n. Our contributions are mostly in efficient implementation of [1] with a canonical decision diagram in such a way that both verification and synthesis of large arithmetic circuits can be more efficient. The experimental results show the effectiveness of our approach in comparison with other decision diagrams and algebraic techniques.

Published in:

High Level Design Validation and Test Workshop (HLDVT), 2011 IEEE International

Date of Conference:

9-11 Nov. 2011