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A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration

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4 Author(s)
J. Wan ; IMEP-LAHC, INP-Grenoble, MINATEC, Grenoble, France ; C. Le Royer ; A. Zaslavsky ; S. Cristoloveanu

We demonstrate experimentally a capacitor-less one-transistor dynamic random access memory (DRAM) based on fully depleted silicon-on-insulator substrate. In our device, the charges are directly stored in front gate capacitor (CG) and read out through a fast feedback regeneration process. The simulated read/write times of our device reach below 1 ns, much faster than conventional 1T-1C DRAM. The read/write biasing voltages can be scaled down to 1.1 V, achieving long retention time (tre >; 5s).

Published in:

IEEE Electron Device Letters  (Volume:33 ,  Issue: 2 )