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A complete methodology for determining memory BIST optimization under wrappers sharing constraints

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3 Author(s)
Zaourar, L. ; SOC Dept., LIP6 Lab., Paris, France ; Kieffer, Y. ; Wenzel, A.

This paper is about a generic method for designing shared memory BIST systems. In order to be of practical use, such a method should work with whatever memory kinds and BIST components are available for the technology used. It should accept arbitrary sharing rules for grouping memories under a wrapper, and it should take individual values of BIST component area, memory test time and memory testing peak power as parameters. We present such a method that uses genetic algorithms for its optimization phase, together with its industrial implementation, and numerical evidence for the value of the method. It is integrated into STMicroelectronics' BIST definition flow.

Published in:

Quality Electronic Design (ASQED), 2011 3rd Asia Symposium on

Date of Conference:

19-20 July 2011