By Topic

Scalability of Extremely Thin SOI (ETSOI) MOSFETs to Sub-20-nm Gate Length

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

14 Author(s)

We report high-performance extremely thin SOI MOSFETs fabricated with a channel thickness down to 3.5 nm, sub-20-nm gate length, and contacted gate pitch of 100 nm. At an effective channel length of 18 nm, a drain-induced barrier lowering of 100 mV is achieved by either thinning the channel to 3.5 nm or by applying a reverse back-gate bias to 6-nm channel MOSFETs. Moreover, minimal increase in series resistance is seen when the channel is scaled to 3.5 nm, resulting in no performance degradation with SOI thickness scaling.

Published in:

Electron Device Letters, IEEE  (Volume:33 ,  Issue: 2 )