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DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function

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4 Author(s)
Lakshminarayana, N.B. ; Georgia Inst. of Technol., Atlanta, GA, USA ; Jaekyu Lee ; Hyesoon Kim ; Jinwoo Shin

GPGPU architectures (applications) have several different characteristics compared to traditional CPU architectures (applications): highly multithreaded architectures and SIMD-execution behavior are the two important characteristics of GPGPU computing. In this paper, we propose a potential function that models the DRAM behavior in GPGPU architectures and a DRAM scheduling policy α-SJF policy to minimize the potential function. The scheduling policy essentially chooses between SJF and FR-FCFS at run-time based on the number of requests from each thread and whether the thread has a row buffer hit.

Published in:

Computer Architecture Letters  (Volume:11 ,  Issue: 2 )