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Nonvolatile ferroelectric polymer memory with controlled hierarchical nanostructures

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3 Author(s)
Kang, S.J. ; Dept. of Mater. Sci. & Eng., Yonsei Univ., Seoul, South Korea ; Park, Y.J. ; Park, C.

In summary, we demonstrated a novel non-volatile ferroelectric polymer transistor memory operating at low voltage with reliable data retention. The nanometer scale periodic trenches of OS lamellae were prepared using block copolymer self assembly and employed as a gate insulator by hybridizing with PVDF-TrFE. Confined crystallization of PVDF-TrFE in the trenches of OS lamellae not only significantly reduces the gate leakage current but also induces effective crystal orientation that facilitates ferroelectric polarization switching. A FeFET consisting of a 1D ribbon type single crystalline TIPS-PEN as an active channel and a hybrid PVDF-TrFE/OS lamellae gate insulator exhibits IDS hysteresis fully that is saturated at a programming voltage as low as ±8 V, ON/OFF current ratio of ~102, and data retention of ~2 hours.

Published in:

Electrets (ISE), 2011 14th International Symposium on

Date of Conference:

28-31 Aug. 2011