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High-throughput pipelined realization of adaptive FIR filter based on distributed arithmetic

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2 Author(s)
Meher, P.K. ; Embedded Syst. Dept., Inst. for Infocomm Res., Singapore, Singapore ; Sang Yoon Park

In this paper, we propose an efficient pipelined architecture for high-speed adaptive filter based on distributed arithmetic (DA). We have shown that the sampling period could be substantially reduced by using carry-save accumulation instead of shift-accumulation for DA-based inner-product implementation for the computation of filter output. Unlike the existing design, the proposed design does not involve any lookup table (LUT). It involves half the number of registers compared to the existing DA-based design to store the sum of different combinations of input samples. The proposed design involves nearly 17% more hardware but offers nearly 7 times throughput and nearly 14 times less energy per sample, in average for filter orders N = 8, 16 and 32 over the existing DA-based design for adaptive filter.

Published in:

VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/IFIP 19th International Conference on

Date of Conference:

3-5 Oct. 2011