By Topic

Positive realization of reduced RLCM nets

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Jorge Fern├índez Villena ; INESC ID / Intituto Superior Técnico - T.U. Lisbon, Rua Alves Redol 9, 1000-029, Portugal ; L. Miguel Silveira

Model Order Reduction is nowadays routinely applied as a basic step in order to enable the efficient simulation of very large RLC linear models, such as extracted parasitics and circuit oriented EM extraction. Often, such reduced models are synthetized as a subcircuit and ported to simulation environments for multiple subsequent runs. Such an approach is quite common as often designers prefer to work with circuit netlists as opposed to abstract mathematical representations and furthermore, many simulators can only handle circuit elements. However, the potential advantages provided by the reduction may be compromised when the dense reduced models are synthetized to netlists due to the presence of non-physical elements (such as negative RLC) or a large number of controlled sources. Such issues may hinder efficiency or even completely preclude analysis as many simulators cannot handle non-physical elements whose handling is altogether questionable. This paper proposes a methodology for the synthesis of reduced order models of general multiport RLC nets amenable to be included in standard simulation environments. Unlike other previously published approaches, the methodology generates very compact models while guaranteeing the positiveness of the RLC values, which allows their direct confinement in any SPICE-like circuit simulator.

Published in:

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip

Date of Conference:

3-5 Oct. 2011