Referenced Items are not available for this document.
In this work we present a design of a massively-parallel cellular processor array implemented in 3D CMOS technology. The proof of concept 128×96 array device is partitioned across two custom designed layers. Additionally, three layers of DDR memory are vertically stacked and bonded underneath. The processor benefits from 358Gbit/s data rate between memory and array, as well as from high logic density, thanks to improved routing across silicon layers with Trough Silicon Vias (TSVs).
Published in:
VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/IFIP 19th International Conference on
Date of Conference: 3-5 Oct. 2011
- Page(s):
- 349 - 353
- E-ISBN :
- 978-1-4577-0169-6
- Print ISBN:
- 978-1-4577-0171-9
- INSPEC Accession Number:
- 12377313
- Conference Location :
- Hong Kong
- Digital Object Identifier :
- 10.1109/VLSISoC.2011.6081606
- Product Type:
- Conference Publications
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