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Multirate hybrid continuous-time/discrete-time cascade 2–2 ΣΔ modulator for wideband telecom

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2 Author(s)
Garcia-Sanchez, J.G. ; Inst. de Microelectron. de Sevilla, Univ. de Sevilla, Sevilla, Spain ; de la Rosa, J.M.

This paper presents the design of a hybrid continuous-time/discrete-time fourth-order cascade ΣΔ modulator intended for wideband low-power wireless applications. The circuit is based on a new concept of multirate operation, in which the front-end stage - implemented using continuous-time (Gm-C) integrators - operates at a higher rate than the back-end (switched-capacitor) stage. This strategy benefits from the faster operation of continuous-time circuits while keeping power efficiency and high robustness against circuit element tolerances. Simulation results show that the modulator is able to operate with a maximum sampling rate of up to 1GHz, digitizing signals with a 44-to-92dB peak signal-to-(noise+distortion) ratio within a programmable 5-to-60MHz bandwidth.

Published in:

VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/IFIP 19th International Conference on

Date of Conference:

3-5 Oct. 2011